 Danila Fedorin
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f317a7e8da
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Add some minor additional sections to report.
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2021-03-17 13:34:04 -07:00 |
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Danila Fedorin
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90a5aed6ec
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Size sense amp back to 40
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2021-03-17 13:12:55 -07:00 |
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Danila Fedorin
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c6d7795074
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Update report with new performance characteristics.
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2021-03-17 13:09:15 -07:00 |
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Danila Fedorin
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d8f4a272e3
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Update to use new wire model's characteristics.
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2021-03-17 13:07:33 -07:00 |
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Danila Fedorin
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ff0edb93bb
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Update with new wire model
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2021-03-17 12:58:36 -07:00 |
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Danila Fedorin
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39ec744562
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Update report.
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2021-03-17 12:21:35 -07:00 |
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Danila Fedorin
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6530e7ef8c
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1.9ns everywhere.
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2021-03-17 12:19:33 -07:00 |
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Danila Fedorin
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71195df7c9
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Add final SRAM design.
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2021-03-17 12:19:17 -07:00 |
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Danila Fedorin
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0c1d8611b1
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Add missing images.
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2021-03-17 12:19:02 -07:00 |
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Danila Fedorin
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b99403a4ff
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Update TODOs.
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2021-03-17 12:16:02 -07:00 |
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Danila Fedorin
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9afa839bff
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Add TODO.
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2021-03-17 11:51:50 -07:00 |
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Danila Fedorin
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6f99879b8f
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Update electric files.
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2021-03-17 09:00:29 -07:00 |
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Danila Fedorin
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fe52f689f9
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Upload files to 'final'
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2021-03-17 00:32:18 -07:00 |
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Danila Fedorin
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c171b0374b
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Upload files to 'final'
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2021-03-17 00:02:13 -07:00 |
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Danila Fedorin
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eb8d068519
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Update 'final/todo.md'
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2021-03-17 00:00:34 -07:00 |
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Danila Fedorin
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6db76f4fd3
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Update todo
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2021-03-16 23:25:36 -07:00 |
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Danila Fedorin
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64ee80be63
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Update report.
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2021-03-16 23:25:30 -07:00 |
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Danila Fedorin
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6b963c967b
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Merge branch 'master' of dev.danilafe.com:ECE-571/Labs
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2021-03-16 19:02:58 -07:00 |
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Danila Fedorin
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4d4ceddcc6
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Update todos
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2021-03-16 19:02:06 -07:00 |
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Danila Fedorin
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75381749d7
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Add initial designs.
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2021-03-16 18:32:56 -07:00 |
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Danila Fedorin
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d2f53a9a4f
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Update 'final/todo.md'
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2021-03-16 18:19:45 -07:00 |
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Danila Fedorin
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0f6426958e
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Update 'final/todo.md'
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2021-03-16 16:47:53 -07:00 |
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Danila Fedorin
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8b9eabdec1
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1.33ns with flip flops and bug mitigation
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2021-03-16 16:30:28 -07:00 |
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Danila Fedorin
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e077bb9071
|
1.35ns with flip flops and bug mitigation
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2021-03-16 16:20:35 -07:00 |
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Danila Fedorin
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76899cb8a3
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2ns with flops.
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2021-03-16 15:44:09 -07:00 |
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Danila Fedorin
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12856ef152
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Use improved senseamp to strengthen performance.
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2021-03-16 14:28:24 -07:00 |
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Danila Fedorin
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ca72f3eb3d
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Rollback to 1.3ns and no write flops.
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2021-03-16 12:22:50 -07:00 |
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Danila Fedorin
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e5b0166d8c
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With flip flops.
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2021-03-15 22:24:43 -07:00 |
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Danila Fedorin
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8ba9d02a8e
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1.24ns
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2021-03-15 16:02:04 -07:00 |
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Danila Fedorin
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c866f63e8c
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1.3 nanoseconds
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2021-03-15 15:17:04 -07:00 |
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Danila Fedorin
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f3ffb39219
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Write-in-middle design.
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2021-03-14 23:11:00 -07:00 |
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Danila Fedorin
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f289e84389
|
Current best effort.
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2021-03-14 21:13:43 -07:00 |
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Danila Fedorin
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5f8a49ab9a
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WIP (still buggy) 2ns design
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2021-03-12 13:53:24 -08:00 |
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Danila Fedorin
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2010fcdf52
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Add initial version of SRAM design.
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2021-03-09 19:15:39 -08:00 |
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Danila Fedorin
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8285087e3f
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Add Scott's various test files.
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2021-03-09 19:15:28 -08:00 |
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Danila Fedorin
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b58f4df33e
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Add my initial definitions of SRAM bits.
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2021-03-09 19:15:07 -08:00 |
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Danila Fedorin
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cf73ec9016
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Add lab 3 sources.
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2021-01-27 15:05:45 -08:00 |
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Danila Fedorin
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a55e55f04f
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Update process script to generate TeX.
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2021-01-27 15:04:23 -08:00 |
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Danila Fedorin
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1ca79fc52b
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Update processing script.
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2021-01-18 13:56:27 -08:00 |
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Danila Fedorin
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b32dfd2a36
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Add required Python packages to git.
|
2021-01-14 20:00:08 -08:00 |
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Danila Fedorin
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a548f96a95
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Add libe writeup and delete useless inages.
|
2021-01-14 19:59:13 -08:00 |
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Danila Fedorin
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5ce4719a1b
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Avoid re-running ltspice
|
2021-01-14 19:57:37 -08:00 |
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Danila Fedorin
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61b22fffdf
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Add lab 2 parameters and simulation script.
|
2021-01-14 19:54:02 -08:00 |
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Danila Fedorin
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b41e616236
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Update lab image.
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2021-01-12 22:19:26 -08:00 |
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Danila Fedorin
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2787981efc
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Add initial drawings of cross section
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2021-01-12 14:25:03 -08:00 |