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ECE-271/VerilogCPU
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Author SHA1 Message Date
Danila Fedorin
5c24d2e464 Update code with new edge detector. 2018-06-07 21:26:46 -07:00
Danila Fedorin
672eae920a Add comments. 2018-06-05 23:42:20 -07:00
Danila Fedorin
d00131973b Add script to generate SPI DO files. 2018-06-05 23:01:13 -07:00
Danila Fedorin
81c9baade2 Add the CPU controller. 2018-06-05 22:57:01 -07:00
Danila Fedorin
bfe4b65788 Fix a port width problem, and change file permissions. 2018-06-05 22:56:46 -07:00
Danila Fedorin
d183a7e1de Add inputs and an instruction to read from them. 2018-06-05 18:58:46 -07:00
Danila Fedorin
c0862e34ba Add an assembly program to demonstrate reading. 2018-06-05 17:36:18 -07:00
Danila Fedorin
39c3fcf9b8 Add help to assembler. 2018-06-05 17:28:24 -07:00
Danila Fedorin
351b23b0f7 Add the basic fibonacci sequence program. 2018-06-05 17:25:12 -07:00
Danila Fedorin
115dce6b8c Write basic assembler. 2018-06-05 17:24:31 -07:00
Danila Fedorin
6bceee5e68 Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00
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