ECE-271/VerilogCPU
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Danila Fedorin 5c24d2e464 Update code with new edge detector.
2018-06-07 21:26:46 -07:00
tasm
Add an assembly program to demonstrate reading.
2018-06-05 17:36:18 -07:00
alu.sv
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2018-06-05 23:42:20 -07:00
assembler.cr
Add help to assembler.
2018-06-05 17:28:24 -07:00
cpu_controller.sv
Update code with new edge detector.
2018-06-07 21:26:46 -07:00
cpu.sv
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2018-06-05 23:42:20 -07:00
edge_detector.sv
Update code with new edge detector.
2018-06-07 21:26:46 -07:00
memory.sv
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2018-06-05 23:42:20 -07:00
mux2.sv
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2018-06-05 23:42:20 -07:00
mux4.sv
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2018-06-05 23:42:20 -07:00
register.sv
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2018-06-05 23:42:20 -07:00
spi_encoder.cr
Add script to generate SPI DO files.
2018-06-05 23:01:13 -07:00
spi_slave.sv
Update code with new edge detector.
2018-06-07 21:26:46 -07:00
Description
A CPU written in SystemVerilog for ECE 271.
212 KiB
Languages
SystemVerilog 51.8%
Crystal 48.2%