DanilaFe/agda-spa
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Author SHA1 Message Date
Danila Fedorin
ffe9d193d9 Parameterize FiniteMap by its keys right away 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 22:19:02 -08:00
Danila Fedorin
cf824dc744 Switch product to using instances 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 21:33:59 -08:00
Danila Fedorin
70847d51db Swich AboveBelow to using instances 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 21:23:07 -08:00
Danila Fedorin
d96eb97b69 Switch maps (and consequently most of the code) to using instances 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 21:16:22 -08:00
Danila Fedorin
d90b544436 Use binary operator for decidable equality consistently 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 19:08:28 -08:00
Danila Fedorin
b0488c9cc6 Make 'IsDecidable' into a record to aid instance search 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 18:58:56 -08:00
Danila Fedorin
8abf6f8670 Make 'isLattice' for simple types be an instance 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2025-01-04 17:27:38 -08:00
Danila Fedorin
4da9b6d3cd Fuse 'FiniteMap' and 'FiniteValueMap' 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-12-31 19:21:23 -08:00
Danila Fedorin
c2c04e3ecd Rewrite Forward analysis to use statement-based evaluators. 
To keep old (expression-based) analyses working, switch to using
instance search and provide "adapters" that auto-construct statement
analyzers from expression analyzers.

Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-12-31 17:31:01 -08:00
Danila Fedorin
f01df5af4b Slightly tweak module style in Forward.agda 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-12-31 12:55:29 -08:00
Danila Fedorin
b28994e1d2 Tighten exported definitions in Forward.agda 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-12-31 00:29:39 -08:00
Danila Fedorin
10332351ea Use instance search to avoid multiply-nested modules 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-12-31 00:21:10 -08:00
Danila Fedorin
9131214880 Slightly clean up import for in-dec for Graph edges 2024-11-16 15:15:42 -08:00
Danila Fedorin
4fba1fe79a Remove unused 'singleton' calls for if/else CFGs 2024-11-16 14:42:16 -08:00
Danila Fedorin
828b652d3b Rename 'a' to 'b' in fixedpoint algorithm proof 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-08-18 10:28:45 -10:00
Danila Fedorin
12971450e3 Add guardedness to Main directly 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-08-08 13:28:25 -07:00
Danila Fedorin
7d2928ed81 Prove that the sign analysis is correct 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-10 22:31:47 -07:00
Danila Fedorin
5f946de5e8 Remove last remaining assumption for correctness 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-10 21:30:56 -07:00
Danila Fedorin
04bafb2d55 Prove that the inputs to wrap are empty 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-10 21:25:40 -07:00
Danila Fedorin
e0248397b7 Prove that predecessors imply edges 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 23:18:51 -07:00
Danila Fedorin
41ada43047 Move predecessor code into Graphs 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 23:13:49 -07:00
Danila Fedorin
a081edb881 Add a proof about filter's distributivity 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 23:06:49 -07:00
Danila Fedorin
3d2a507f2f Almost prove correctness 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 22:49:53 -07:00
Danila Fedorin
82027ecd04 Move predecessor computation into Graphs 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 21:26:32 -07:00
Danila Fedorin
734e82ff6d Wrap generated graphs to ensure entry and exit nodes have no extra edges 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 21:08:32 -07:00
Danila Fedorin
69d1ecebae Prove that the bottom map's valyes are all bottoms 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 20:48:32 -07:00
Danila Fedorin
b78cb91f2a Strengthen lemma about IterProd bottom to definition equality 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 20:20:11 -07:00
Danila Fedorin
16fa4cd1d8 Use records rather than nested pairs to represent 'fixed height' 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 20:11:04 -07:00
Danila Fedorin
95669b2c65 Prove that the iterated product is made from iterated bottom elements 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 19:45:15 -07:00
Danila Fedorin
6857f60465 Rename the min/max elements top bottom and top in Prod 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 19:08:46 -07:00
Danila Fedorin
f4392b32c0 Finish the last proof obligation for trace walking 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 19:01:36 -07:00
Danila Fedorin
794c04eee9 Prove the foldr-implies lemma 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 18:37:50 -07:00
Danila Fedorin
80069e76e6 Prove the recursive step of trace walking 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 17:56:47 -07:00
Danila Fedorin
a22c0c9252 Prove a property of multi-key lookup 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 17:56:26 -07:00
Danila Fedorin
20dc99ba1f Re-indent some code to take up less horizontal space 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 16:57:03 -07:00
Danila Fedorin
b3a62da1fb Add a proof that edges lead to 'incoming' inclusion 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-09 16:56:45 -07:00
Danila Fedorin
f0b0d51b48 Add unproven lemma about fold implication 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 23:38:23 -07:00
Danila Fedorin
8ff88f9f9e Move helper code into separate function 
I'll need to reuse it.

Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 23:35:02 -07:00
Danila Fedorin
c1581075d3 Add more test programs 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 23:30:23 -07:00
Danila Fedorin
838aaf9c58 Start end-to-end proof of correctness 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 23:30:03 -07:00
Danila Fedorin
4ac9dffa9b Prove that the var->lattice maps respect equality 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 22:53:21 -07:00
Danila Fedorin
3f5551d70c Add a lemma about the effect of joinAll 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 22:34:02 -07:00
Danila Fedorin
5837fdf19b Prove that 'updateAll' has preservation 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 22:29:36 -07:00
Danila Fedorin
4350919871 Add proof about setVariablesForState 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 22:09:56 -07:00
Danila Fedorin
7fe46b014c Slightly simplify evaluation code 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 22:05:50 -07:00
Danila Fedorin
66d229c493 Prove that multi-statement evaluation "preserves" the validity of the analysis 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 21:51:53 -07:00
Danila Fedorin
1b8bea8957 Use foldl in multi-statement evaluation 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 21:50:38 -07:00
Danila Fedorin
dd8cdcd10c Add proofs about monotonicity of foldl 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 21:48:41 -07:00
Danila Fedorin
ad4592d4d2 Switch to using implicit arguments where needed 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 21:34:17 -07:00
Danila Fedorin
8d0d87d2d9 Start on proofs of correctness 
Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>
 2024-05-08 20:50:21 -07:00